4位元多工器 不是合併的

module top;

wire A0, A1, A2, A3, B0, B1, B2, B3, OUT, SEL;

system_clock #12800 clock1(A0);
system_clock #6400  clock2(A1);
system_clock #3200  clock3(A2);
system_clock #1600  clock3(A3);
system_clock #800   clock4(B0);
system_clock #400   clock5(B1);
system_clock #200   clock6(B2);
system_clock #100   clock7(B3);
system_clock #50    clock8(SEL);

and a1 (c1,A0,SEL);
and a2 (c2,A1,SEL);
and a0 (c0,A2,SEL);
and a6 (c6,A3,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B0);
and a4 (c4,cn,B1);
and a5 (c5,cn,B2);
and a7 (c7,cn,B3);
or o0 (OUT1,c1,c3);
or o1 (OUT2,c2,c4);
or o2 (OUT3,c5,c0);
or o3 (OUT4,c6,c7);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule