4位元多工器 不是合併的

module top;

wire A0, A1, A2, A3, B0, B1, B2, B3, OUT, SEL;

system_clock #12800 clock1(A0);
system_clock #6400  clock2(A1);
system_clock #3200  clock3(A2);
system_clock #1600  clock3(A3);
system_clock #800   clock4(B0);
system_clock #400   clock5(B1);
system_clock #200   clock6(B2);
system_clock #100   clock7(B3);
system_clock #50    clock8(SEL);

and a1 (c1,A0,SEL);
and a2 (c2,A1,SEL);
and a0 (c0,A2,SEL);
and a6 (c6,A3,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B0);
and a4 (c4,cn,B1);
and a5 (c5,cn,B2);
and a7 (c7,cn,B3);
or o0 (OUT1,c1,c3);
or o1 (OUT2,c2,c4);
or o2 (OUT3,c5,c0);
or o3 (OUT4,c6,c7);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

三位元多工器 1+2合併

module top;

wire [2:0]A, B, OUT;
wire SEL;
system_clock #3200 clock1(A[0]);
system_clock #1600 clock2(A[1]);
system_clock #800  clock3(A[2]);
system_clock #400  clock4(B[0]);
system_clock #200  clock5(B[1]);
system_clock #100  clock6(B[2]);
system_clock #50   clock7(SEL);


mux3 mi(OUT, A, B, SEL);

endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule



module mux3(OUT, A, B, SEL);
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux middle(OUT[2], A[2], B[2], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;


endmodule

二位元多工

module top;

wire A1, A0, B1, B0, SEL, OUT1, OUT2
system_clock #100 clock1(A1);
system_clock #200 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #800 clock4(B1);
system_clock #1600 clock5(B0);

and a1 (c1,A1,SEL);
and a2 (c2,A0,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B1);
and a4 (c4,cn,B0);
or o1 (OUT1,c1,c3);
or o2 (OUT2,c2,c4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule

1位元

第三次上課

module top;

system_clock #400 clock1(A);

system_clock #200 clock2(B);

system_clock #100 clock3(SEL);

mux M1(OUT, A, B, SEL);

endmodule


module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule           課本範例1                  2015.10.7