二位元多工

module top;

wire A1, A0, B1, B0, SEL, OUT1, OUT2
system_clock #100 clock1(A1);
system_clock #200 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #800 clock4(B1);
system_clock #1600 clock5(B0);

and a1 (c1,A1,SEL);
and a2 (c2,A0,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B1);
and a4 (c4,cn,B0);
or o1 (OUT1,c1,c3);
or o2 (OUT2,c2,c4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule