期末考

module top;
system_clock #400 clock1(a);
system_clock #200 clock1(a);
system_clock #100 clock1(a);
system_clock #50 clock1(a);
number n1(e,a,b,c,d);
endmodule
module number(e1,a,b,c,d);
input a,b,c,d;
output e1;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5,h1,h2,h3,h4,h5,g1,g2,g3,g4,g5;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(h1,a1,b1,c);
nand(w1,h1,h1);
nand(h2,a,b1,c1);
nand(w2,h2,h2);
nand(h3,a,b,c1);
nand(w3,h3,h3);
nand(h4,a1,b,c1,d);
nand(w4,h4,h4);
nand(h5,a,b,c,d);
nand(w5,h5,h5);
nand(g1,w1,w1);
nand(g2,w2,w2);
nand(g3,w3,w3);
nand(g4,w4,w4);
nand(g5,w5,w5);
nand(e1,g1,g2,g3,g4,g5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

三位元全加法器

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

一位元全多公器

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
                $display(" 1+0+0=01 sum is WRONG!");
              else
                $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 1 | sum !== 0)
                $display(" 1+1+0=10 sum is WRONG!");
              else
                $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
                $display(" 1+1+1=11 sum is WRONG!");
              else
                $display(" 1+1+1=11 sum is RIGHT!");


    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

二位元 行為

  odule top;
  integer ia0,ia1,ib0,ib1,is;
  reg  a0,a1,b0,b1,s;
  wire out1,out2

  mux_behavioral mux1(out1,out2,a0,a1,b0,b1,s);

  initial
    begin
      for (ia0=0; ia0<=1; ia0 = ia0+1)
        begin
          a0 = ia0;
          for (ia1=0; ia1<=1; ia1 = ia1+ 1)
            begin
              a1 = ia1;
               for (ib0=0; ib0<=1; ib0 = ib0+1)
                 begin
                   b0 = ib0;
                   for (ib1=0; ib1<=1; ib1 = ib1+ 1)
                    begin
                     b1 = ib1;
                      for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #100 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);
                       end
                    end
                  end
              end
         end
   end
endmodule

module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL)
 output OUT1,OUT2;
 input A0,A1,B0,B1,SEL;
 wire  A0,A1,B0,B1,SEL;
 reg   OUT1,OUT2;

always @(A0 or A1 or B0 or B1 or SEL)
 begin
   OUT1 = (A0 & SEL)|(B0 & ~SEL );
   OUT2 = (A1 & SEL)|(B1 & ~SEL );
 end
endmodule

4位元多工器 不是合併的

module top;

wire A0, A1, A2, A3, B0, B1, B2, B3, OUT, SEL;

system_clock #12800 clock1(A0);
system_clock #6400  clock2(A1);
system_clock #3200  clock3(A2);
system_clock #1600  clock3(A3);
system_clock #800   clock4(B0);
system_clock #400   clock5(B1);
system_clock #200   clock6(B2);
system_clock #100   clock7(B3);
system_clock #50    clock8(SEL);

and a1 (c1,A0,SEL);
and a2 (c2,A1,SEL);
and a0 (c0,A2,SEL);
and a6 (c6,A3,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B0);
and a4 (c4,cn,B1);
and a5 (c5,cn,B2);
and a7 (c7,cn,B3);
or o0 (OUT1,c1,c3);
or o1 (OUT2,c2,c4);
or o2 (OUT3,c5,c0);
or o3 (OUT4,c6,c7);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

三位元多工器 1+2合併

module top;

wire [2:0]A, B, OUT;
wire SEL;
system_clock #3200 clock1(A[0]);
system_clock #1600 clock2(A[1]);
system_clock #800  clock3(A[2]);
system_clock #400  clock4(B[0]);
system_clock #200  clock5(B[1]);
system_clock #100  clock6(B[2]);
system_clock #50   clock7(SEL);


mux3 mi(OUT, A, B, SEL);

endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule



module mux3(OUT, A, B, SEL);
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux middle(OUT[2], A[2], B[2], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;


endmodule

二位元多工

module top;

wire A1, A0, B1, B0, SEL, OUT1, OUT2
system_clock #100 clock1(A1);
system_clock #200 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #800 clock4(B1);
system_clock #1600 clock5(B0);

and a1 (c1,A1,SEL);
and a2 (c2,A0,SEL);
not N1 (cn,SEL);
and a3 (c3,cn,B1);
and a4 (c4,cn,B0);
or o1 (OUT1,c1,c3);
or o2 (OUT2,c2,c4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule